The present invention relates to a method for fabricating MOS transistors with LDD regions, wherein the series resistance of the LDD regions is maintained by retarding dopant segregation into an overlying liner oxide layer, and to MOS transistors obtained thereby. The method has particular utility in the manufacture of high speed integrated circuit (IC) semiconductor devices.
The escalating requirements for high integration density and performance associated with ultra-large scale (xe2x80x9cULSIxe2x80x9d) integration semiconductor devices are difficult to satisfy in terms of achieving pre-selected, or desired, device characteristics, including, inter alia, drive currents and series resistance of LDD portions of source and drain regions of MOS transistors. As a consequence of such difficulty in achieving desired device characteristics, significant device rejection rates may be experienced in large-scale manufacture, leading to increased cost.
According to methodology currently employed in the manufacture of MOS transistors, a thin gate oxide layer and an overlying gate electrode layer, typically a polysilicon layer, are formed over the surface of a semiconductor substrate, followed by selective removal processing, as by anisotropic etching, to define a gate electrode/gate oxide layer stack overlying a portion of the substrate surface. LDD regions which extend for a short distance beneath the side edges of the gate electrode/gate oxide layer stack are then formed to a shallow depth in portions of the substrate not covered by the gate electrode/gate oxide layer stack, typically by implantation of dopant-containing ions, utilizing the gate electrode/gate oxide layer stack as an implantation mask. A thin liner oxide layer is then formed over the exposed portions of the substrate surface, i.e., the just-formed LDD regions, and over the side edge and top surfaces of the gate electrode/gate oxide layer stack. Insulative sidewall spacers are then formed on the portions of the thin liner oxide layer covering the side edge surfaces of the gate electrode/gate oxide layer stack and adjacent portions of the substrate surface, as by depositing a blanket layer of an electrically insulative material, e.g., a silicon oxide or nitride, over each of the exposed surfaces, followed by selectively anisotropically etching the blanket layer. More heavily-doped source and drain regions are then formed in the respective LDD regions at a deeper level below the substrate surface, as by implantation of dopant-containing ions, utilizing the gate electrode/gate oxide layer stack with sidewall spacers thereon as an implantation mask. A thermal annealing process is then performed in order to activate the implanted dopant species and effect source/drain junction formation.
A drawback associated with the above-described conventional process scheme for MOS transistor formation is the tendency for the dopant species to upwardly move from LDD regions in silicon (Si) and segregate in the overlying thin liner oxide layer, thereby resulting in dopant concentrations in the LDD regions which are less than desired or optimal. As a consequence, the series resistance of the LDD regions is greater than the design value therefor, and the device drive current is disadvantageously decreased. The effect of dopant movement from the LDD regions upwardly into the overlying thin liner oxide layer is especially significant when p-doped LDD regions are formed by implantation of boron (B) ions or indium (In) ions.
In view of the foregoing, there exists a need for methodology enabling the formation of microelectronic devices, e.g., MOS transistors and MOS transistor-based devices, such as CMOS devices, which enables a substantial and significant reduction in the tendency for dopant segregation in thin liner oxide layers overlying LDD regions, whereby disadvantageous increase in the series resistance of the LDD regions and decreased drive currents of the MOS transistors are effectively prevented, or at least minimized.
The present invention, wherein a species which effectively retards movement of dopant species from LDD regions into overlying, thin liner oxide layers, is incorporated in the thin liner oxide layers, effectively addresses and solves the problems of increased series resistance and decreased device drive current associated with the conventional MOS transistor fabrication methodology, while maintaining full compatibility with all other aspects of conventional technology for automated manufacture of microelectronic devices such as IC devices. Further, the methodology afforded by the present invention can be readily and easily implemented in cost-effective manner utilizing conventional deposition/implantation techniques. Finally, the methodology of the present invention enjoys diverse utility in the manufacture of numerous and various types of semiconductor devices and/or components.
An advantage of the present invention is an improved method of manufacturing a semiconductor device.
Another advantage of the present invention is an improved method of manufacturing a MOS transistor device.
Still another advantage of the present invention is an improved method of manufacturing a MOS transistor device comprising boron (B)-doped or indium (In)-doped LDD regions.
A still further advantage of the present invention is an improved semiconductor device.
A yet another advantage of the present invention is an improved MOS transistor device.
An additional advantage of the present invention is an improved MOS device comprising boron (B)-doped or indium (In)-doped LDD regions.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the present invention may be realized as particularly pointed out in the appended claims.
According to an aspect of the present invention, the foregoing and other advantages are obtained in part by a method of manufacturing a semiconductor device, comprising steps of:
(a) providing a semiconductor substrate including at least one dopant species-containing region extending to a surface of the substrate;
(b) forming a thin liner oxide layer on the surface of the substrate; and
(c) incorporating in the thin line oxide layer at least one species which substantially prevents, or at least reduces, segregation therein of the dopant species arising from movement thereinto from the at least one dopant species-containing region.
According to alternative embodiments of the present invention, steps (b) and (c) are performed simultaneously, or steps (b) and (c) are performed sequentially in the recited order.
In accordance with certain embodiments of the present invention, step (a) comprises providing a silicon (Si)-based semiconductor substrate including at least one p-type or n-type dopant species-containing region extending to a surface of said substrate; step (b) comprises forming a thin liner oxide layer comprised of a silicon oxide; and step (c) comprises implanting the thin liner oxide layer with ions of at least one species which substantially prevents, or at least reduces, segregation therein of the dopant species arising from movement thereinto from the at least one dopant species-containing region.
According to particular embodiments of the present invention, step (a) comprises providing a Si-based semiconductor substrate including at least one boron (B)-doped or indium (In)-doped p-type region extending to a surface of the substrate; and step (c) comprises implanting at least one of nitrogen (N)-containing and germanium (Ge)-containing ions in the thin liner oxide layer.
In accordance with preferred embodiments of the present invention, step (a) comprises providing a semiconductor substrate including:
(i) a thin gate insulator layer in overlying contact with a portion of the substrate surface;
(ii) an electrically conductive gate electrode in overlying contact with the thin gate insulator layer, the gate electrode comprising first and second opposing side surfaces and a top surface; and
(iii) a pair of spaced-apart, shallow-depth, lightly-doped source and drain regions, each of the source and drain regions extending in the substrate to just beneath a respective proximal edge of the gate electrode;
step (b) comprises forming a thin conformal liner oxide layer in overlying contact with the substrate surface and the first and second opposing side surfaces and the top surface of the gate electrode; and
step (c) comprises incorporating in the thin liner oxide layer ions of at least one species which substantially prevents, or at least reduces, segregation therein of dopant species arising from movement thereinto from the pair of lightly-doped source and drain regions.
According to the preferred embodiments of the invention, step (a) comprises providing a silicon (Si)-based substrate; the thin gate insulator layer (i) comprises a silicon oxide layer, a silicon nitride layer, or a silicon nitride/silicon oxide layer stack; the electrically conductive gate electrode (ii) comprises polysilicon; and step (b) comprises forming a thin conformal liner oxide layer comprising a silicon oxide; wherein: step (a) comprises providing a Si substrate wherein the pair of spaced-apart, shallow-depth, lightly-doped source and drain regions are boron (B)-doped or indium (In)-doped p-type regions; and step (c) comprises incorporating at least one of nitrogen (N)-containing and germanium (Ge)-containing ions in the thin liner oxide layer.
According to particular embodiments of the present invention, step (b) comprises forming the thin conformal liner oxide layer to a thickness from about 40 to about 400 xc3x85; and step (c) comprises implanting at least one of nitrogen (N)-containing and germanium (Ge)-containing ions in the thin liner oxide layer, e.g., step (c) comprises implanting at least one of nitrogen (N)-containing and germanium (Ge)-containing ions at energies between about 1 and about 15 KeV and dosages between about 5xc3x971014/cm2 and 3xc3x971015/cm2, depending upon the liner oxide thickness and implantation species.
Another aspect of the present invention is a method of manufacturing a MOS transistor, comprising steps of:
(a) providing a semiconductor substrate having a surface and including:
(i) a thin gate insulator layer in overlying contact with a portion of the substrate surface;
(ii) an electrically conductive gate electrode in overlying contact with the thin gate insulator layer, the gate electrode comprising first and second opposing side surfaces and a top surface; and
(iii) a pair of spaced-apart, shallow-depth, lightly-doped source and drain extension regions, each of the source and drain extension regions extending in the substrate to just beneath a respective proximal edge of the gate electrode;
(b) forming a thin conformal liner oxide layer in overlying contact with the substrate surface and the first and second opposing side surfaces and the top surface of the gate electrode; and
(c) incorporating in the thin liner oxide layer at least one species which substantially prevents, or at least reduces, segregation therein of dopant species arising from movement thereinto from the pair of source and drain extension regions.
According to embodiments of the present invention, the method further comprises steps of:
(d) forming insulative sidewall spacers on the first and second opposing side surfaces of the gate electrode;
(e) forming deeper, more heavily-doped source and drain regions below the respective shallow-depth, lightly-doped source and drain extension regions; and
(f) thermally annealing the source and drain regions to activate dopant species therein and effect source and drain junction formation.
In accordance with certain embodiments of the invention, step (e) comprises forming the deeper, more heavily-doped source and drain regions by dopant ion implantation using the insulative sidewall spacers as implantation masks.
According to preferred embodiments of the present invention,
step (a) comprises providing a silicon (Si)-based substrate; the thin gate insulator layer (i) comprises a silicon oxide layer, a silicon nitride layer, or a silicon nitride/silicon oxide layer stack; the electrically conductive gate electrode (ii) comprises polysilicon; the pair of spaced-apart, shallow-depth, lightly-doped source and drain extension regions (iii) are boron (B)-doped or indium (In)-doped p-type regions;
step (b) comprises forming a thin conformal liner oxide layer comprising a silicon oxide; and
step (c) comprises incorporating at least one of nitrogen (N)-containing and germanium (Ge)-containing ions in the thin liner oxide layer; e.g., step (b) comprises forming the thin conformal liner oxide layer to a thickness from about 40 to about 400 xc3x85; and step (c) comprises implanting at least one of nitrogen (N)-containing and germanium (Ge)-containing ions in the thin liner oxide layer at energies between about 1 and about 15 KeV and dosages between about 5xc3x971014/cm2 and 3xc3x971015/cm2.
Yet another aspect of the present invention is a semiconductor device, comprising:
(a) a semiconductor substrate including at least one dopant species-containing region extending to a surface of the substrate; and
(b) a thin liner oxide layer on the surface of the substrate, wherein the thin line oxide layer includes at least one species which substantially prevents, or at least reduces, segregation therein of the dopant species arising from movement thereinto from the at least one dopant species-containing region.
According to embodiments of the present invention, the semiconductor substrate (a) is a silicon (Si)-based substrate, the at least one dopant species-containing region is a boron (B)-doped or indium (In)-doped p-type region; the thin liner oxide layer (b) is a silicon oxide layer, and the at least one species which substantially prevents, or at least reduces, segregation therein of the dopant species arising from movement thereinto from the at least one dopant species-containing region is at least one of nitrogen (N)-containing and germanium (Ge)-containing species.
In accordance with preferred embodiments of the present invention, the semiconductor device is a MOS transistor and the semiconductor substrate (a) includes:
(i) a thin gate insulator layer in overlying contact with a portion of the substrate surface;
(ii) an electrically conductive gate electrode in overlying contact with the thin gate insulator layer, the gate electrode comprising first and second opposing side surfaces and a top surface; and
(iii) a pair of spaced-apart, shallow-depth, lightly boron (B)-doped or indium (In)-doped source and drain extension regions, each of the source and drain extension regions extending in the substrate to just beneath a respective proximal edge of the gate electrode; and the thin liner oxide layer (b) is a conformal layer in overlying contact with the substrate surface and the first and second opposing side surfaces and the top surface of the gate electrode; wherein the semiconductor substrate (a) further includes:
(iv) deeper, more heavily-doped source and drain regions below the respective shallow-depth, lightly-doped source and drain extension regions; and
insulative sidewall spacers on the first and second opposing side surfaces of the gate electrode.
Additional advantages and aspects of the present invention will become apparent to those skilled in the art from the following detailed description, wherein embodiments of the present invention are shown and described, simply by way of illustration of the best mode contemplated for practicing the present invention. As will be described, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as limitative.